PD-FORGE links every report from every stage, run and tool to the same nets, cells and paths. When a violation shows up at signoff, it traces it back to the stage that caused it.
In closed testing. Production in Q4 2026.
Today your QoR sits in separate reports for each tool, stage and run. PD-FORGE ties it all to the same nets, cells, clocks and paths, and learns from every run. It is the physical design counterpart of the SoC mental map behind DV-FORGE.
Violations show up late but start early. PD-FORGE narrows gigabytes of reports to the violation’s cone and traces it back through past stages, deterministically, before an LLM is asked anything. It is the cone-of-influence idea behind DV-FORGE, applied to physical design.
The same failing path, as three kinds of tool would report it.
what you getrun_23 finished.
WNS −0.41 ns, TNS −11.2 ns.
9 DRC violations.
Tells you it failed.
what you getTiming failed on some paths, likely due to congestion. Consider increasing routing effort.
Guesses from a log too big to read.
what you getRoot cause at CTS: 11 clock buffers in gcell (41,17) made 2 nets detour 1.34× at route. Seen in run 22, fixed there by a CTS blockage.
Innovus cts/place.rpt:88PrimeTime timing.rpt:48
Tells you why, where, and what fixed it before.
The same correlation answers everyday QoR questions across runs and tools, and watches your runs so you do not have to babysit them.
Without PD-FORGE:
Fewer iterations, fewer repeated mistakes, signoff sooner.
Synopsys, Cadence, Siemens and open-source flows in one place. PD-FORGE drives your tools and replaces none of them.
Fusion Compiler
Innovus
IC Compiler II
Aprisa
OpenROAD
PrimeTime
Tempus
PrimeClosure
OpenSTA
Design Compiler
Genus
Tessent
Conformal
Yosys
Calibre
Pegasus
IC Validator
StarRC, Quantus
RedHawk-SC
Swadeza collaborates with professors at BIT Patna and with Signitude, a fabless semiconductor company.
academic collaborationBIT PatnaProfessors of the Birla Institute of Technology, Patna campus
industry collaborationSignitudeFabless semiconductor company
Also from Swadeza: DV-FORGE, the same approach for verification, which signed off OpenTitan Earlgrey, a taped-out root-of-trust SoC, in 30 days, most of it in regression.
PD-FORGE is in closed testing, with production in Q4 2026. Talk to us about early access, a deployment or a collaboration.