FORGESpec, RTL, layout, silicon: forged into one.
FORGE is Swadeza’s end-to-end suite for verification, physical design, post-silicon validation and standard cells, deployed on-premises. Each workflow keeps your chip in a cited map, sends an LLM only what a question touches, and turns what it learns into deterministic models, so each run finishes sooner and costs less than the last.
FORGE is Swadeza’s end-to-end suite for verification, physical design, post-silicon validation and standard cells, deployed on-premises.
* Most of these days were spent in regression.
Explore DV-FORGEFrom the specification to debugged silicon, every phase your team owns has an AI-native FORGE workflow, all built on the same map-and-cone engine and all deployed on-premises. Only fabrication stays with your foundry.
DeliveredClosed testingIn development
Spec to verification signoff
Delivered
Your whole SoC, signed off in days.
OpenTitan Earlgrey, a taped-out root-of-trust SoC, signed off in 30 days*, and Darjeeling, the next chip in its family, in 21*.
* Most of these days were spent in regression.
Explore DV-FORGESynthesis to signoff
Closed testing, production Q4 2026
Close your block in fewer iterations.
Every report from every stage, run and tool linked to the same nets, across 26 Synopsys, Cadence, Siemens and open-source back-ends.
Explore PD-FORGEPost-silicon validation and debug
In development
Validate and debug silicon the way DV-FORGE verifies RTL.
It generates the validation plan and tests from the map of the chip, and debugs each failure on silicon through its cone to the block and register behind it.
Contact us about PS-FORGEThe cells every design is built from
In development
The best possible cell, with a mathematical guarantee.
Give it an existing standard cell and your design constraints. It returns the optimal cell under those constraints, and proves no better one exists.
A standard cell repeats across millions of instances, so any reduction in it goes directly to gross margin.
Contact us about SC-FORGEOur first public demonstration of FORGE is at SEMICON India in New Delhi. Walk over to startup pod 6 and see it run.
We are at the show now. Walk over to startup pod 6 in Yashobhoomi and see FORGE run.
Thank you for stopping by. Write to us with what you work on, and we will reply with a next step for your team.
The show opens on 17 September.
Can’t make it to New Delhi? Reach us at info@swadeza.com.
Professors of the Birla Institute of Technology, Patna campus.
A fabless semiconductor company.
Also from Swadeza: the first fully automated in-production AI verification and validation system for government recruitment, built for the Government of Bihar.
On-premises deployments, early access, collaborations, PS-FORGE, SC-FORGE or a question about your own flow: write to us and the team will get back to you.
info@swadeza.com